1. Field of the Invention
The present invention relates to a fault model and rule based fault management apparatus and method for a home network and, more particularly, to a fault model and rule based fault management apparatus and method for improving the reliability of a home network and reducing a maintenance cost of a home network by defining fault models for possible faults generated from various fault generation apparatus distributed in a home network, such as a device, a network, a system, and an application program, defining fault decision rules for diagnosing a cause of a fault, defining fault process rules for each cause, and diagnosing and processing a fault based on the defined fault model, the defined fault decision rules, and the defined fault process rules when the fault is generated in a home network.
This work was supported by the Information Technology (IT) research and development program of the Korean Ministry of Information and Communication (MIC) and/or the Korean Institute for Information Technology Advancement (IITA) [2006-S-066-01, “Development of High Reliable Adaptive Middleware for u-Home”].
2. Description of Related Art
According to the abrupt development of a home network technology, there have been many studies in progress for developing a method for managing faults generated in a home network. A home network has a characteristic of a complex system where various devices and software are distributed over the entire home network.
Hereinafter, a fault management technology for a home network according to the related art will be described with reference to FIG. 1.
FIG. 1 is a block diagram illustrating a fault management apparatus for sensing faults and performing restoration according to the related art.
As shown in FIG. 1, the fault management apparatus according to the related art includes a watchdog controlling unit 20, and a watchdog generating unit 30. A processor 10 processes data in hardware manner. The watch dog controlling unit 20 controls general restoration operations by outputting a sensing signal WD_ST for the processor 10 to the watchdog generating unit 30 and outputting a Non Maskable Interrupt (NMI) to the processor 10 when receiving a first time out signal from the watchdog generating unit 30. The watchdog generating unit 30 determines that the processor 10 is in an abnormal state if the watchdog generating unit 30 does not receive a sensing signal WD_ST from the watchdog controlling unit 20 within a predetermined interval. Then, the watchdog generating unit 30 generates a first timeout signal to the watchdog controlling unit 20.
Here, the watchdog controlling unit 20 includes a watchdog state register 21 for providing watchdog information to the process 10. Also, the watchdog generating unit 30 includes a watchdog timer 31.
The fault management apparatus according to the related art will be described in more detail. The watchdog controlling unit 20 generates a sensing signal WD_ST and outputs the generated sensing signal WD_ST to the watchdog generating unit 30 at a predetermined interval which is set by the processor 10. If the watchdog generating unit 30 does not receive the sensing signal WD_ST from the watchdog controlling unit 20 within the predetermined interval, the watchdog generating unit 30 outputs the first timeout signal to the watchdog controlling unit 20. Accordingly, the watchdog controlling unit 20 outputs the Non Maskable Interrupt (NMI) to the processor 10 to perform the restoration operation.
After outputting the first timeout signal, if the watchdog generating unit 30 does not receive the sensing signal WD_ST within a predetermined interval again, the watchdog generating unit 30 outputs a second timeout signal to the watchdog controlling unit 20. Then, the watchdog controlling unit 20 determines that the processor 10 is in a malfunction state where the restoration is unable and resets the processor 10.
As described above, if a hardware board with a processor mounted malfunctions or if software generates endless loop due to a program fault, the fault management apparatus according to the related art generates the Non Maskable Interrupt (NMI) before resetting the processor in order to restore the processor from an abnormal state to a normal state. If the abnormal state is sustained, the fault management apparatus according to the related art resets the processor through board resetting.
As described above, the fault management technology according to the related art only considers the abnormal state of a processor and the endless loop state of software. Therefore, the fault management technology according to the related art is not suitable for a complex system like a home network where faults are generated from various devices although the fault management technology according to the related art is applicable to a simple system.